Decomposition of BDDs with Application to Physical Mapping of Regular PTL Circuits

Non-Crossing Ordered BDDs (NCOBDDs) [3], were proposed for mapping to pass transistor logic (PTL) circuits with very high performance and regular layout. However, the latency and area penalty prevents it to be applied to large circuits. In this paper, we propose a dynamic-programming based approach for decomposition of BDDs. The decomposed BDDs can be applied to construct more compact NCOBDDs that have lower latency, area, and power than the monolithic ones. Experimental results show that, on average, the decomposed NCOBDDs can reduce the latency by 45%, and reduce the area by 53%, respectively.